Answers Database
M1.4 LogiBLOX: Discrepancy between Dual Port RAM simulation behavior and Dynatext documentation.
Record #3265
Product Family: Documentation
Product Line: FPGA Core
Product Part: docs
Problem Title:
M1.4 LogiBLOX: Discrepancy between Dual Port RAM simulation behavior and Dynatext
documentation.
Problem Description:
In the (Dynatext) LogiBLOX Reference/User Guide book, the
function of the DPO pin on dual port RAMS is described as
follows:
DPO
The Dual Port Output is used to output the data that occurs on
the Dual Port Read Address input of the DP_RAM module whenever
Write Enable Clock goes High.
Although this is not incorrect, it is misleading.
Solution 1:
The statement in the book is true if you are writing to the
location that is currently being read, i.e., after a delay,
the value written into that location will appear on DPO.
However, in general, you usually do not write to the
same location you read from.
The value on DPO also changes depending on the value of the
address bus DPRA. When this is stable, after a delay. the data
in that part of the RAM cell appears on DPO. This allows data
to be read from the RAM independently from the write strobe.
This feature is not clear from the current documentation.
End of Record #3265 - Last Modified: 07/10/98 14:02 |
