Answers Database


XC4000XL/XV: XV vs XL Architectural Differences


Record #3283

Product Family: Hardware

Product Line: 4000

Product Part: 4000XV

Problem Title:
XC4000XL/XV: XV vs XL Architectural Differences


Problem Description:
FCLK: Similar to the EX/XL architecture, the XV devices have an FCLK along the left
    and right edge of the device. The main difference lies in its implementation. In the XL
    devices, one of the two paths I1, I2 in the IOB is used for the FCLK. However, in the
    XV devices the FCLK path is independent of I1 and I2. The FCLK path is programmed
    in the bitstream such that the I1, I2 and FCLK paths are mutually exclusive. This is
    done by using an unused combination of the 2 bits used to program the MUXES in the I1,I2
    paths to program the FCLK path. This feature has been added primarily for speed.


5V PCI in the IOBs: From a circuit viewpoint, a 5V PCI drive in the IOBs essentially
    means added drive in the IOBs. This is accomplished by increasing the drive of the IOB
    by an additional parallel buffer controlled by a configuration bit. This implies a
    bitstream change. For all IOBs except the center IOB on the left side this configuration
    bit is an unused bit from the XL bitstream. For the center IOB on the left side, this

    bit happens to be the charge-pump control bit. Since the charge pump is not being used
    in either the XL or the XV this bit does not pose any new functionality in the
    XV. Buffered TBUF long lines: In the XL architecture, the TBUF Horizontal Long Line
    has 5 pips per tile that allow for the TBUF HLL to drive inputs. These pips are
    unbuffered in the XL architecture. In the XV architecture, these pips are buffered from
    the TBUF HLL by a single buffer. The buffer drives a segment with these 5 pips as
    shown below.


Solution 1:






End of Record #3283 - Last Modified: 01/16/98 00:48

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!