Answers Database
Foundation XVHDL: Instantiating OSC52 in a 5200 design
Record #3339
Product Family: Software
Product Line: Metamor
Product Part: Foundation XVHDL
Problem Title:
Foundation XVHDL: Instantiating OSC52 in a 5200 design
Problem Description:
Urgency: Standard
General Description:
How do you instantiate the OSC52 in a 5200 XVHDL design?
The code is given below.
Solution 1:
--The following is an example of instantiating the OSC52
library IEEE,metamor;
use IEEE.std_logic_1164.all;
use metamor.attributes.all;
entity OSC5_INST is port (
output : out STD_LOGIC
); end OSC5_INST;
architecture rtl of OSC5_inst is
--COMPONENT Declarations
component OSC52 port (
OSC1 : out STD_LOGIC;
OSC2 : out STD_LOGIC);
end component;
component FD port (
C : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC);
end component;
attribute DIVIDE1_BY : string;
attribute DIVIDE2_BY : string;
attribute DIVIDE1_BY of U1 : label is "4"; --You can adjust
attribute DIVIDE2_BY of U1 : label is "2"; --You can adjust
--SIGNALS
signal osc1_out : STD_LOGIC;
signal osc2_out : STD_LOGIC;
signal outbuf : STD_LOGIC;
begin
--SIGNAL ASSIGNMENTS
output <= outbuf;
--COMPONENT INSTANTIATIONS
U1 : OSC52 port map(
OSC1 => osc1_out,
OSC2 => osc2_out
);
u2 : FD port map(
C => osc1_out,
D => osc2_out,
Q => outbuf
);
end rtl;
End of Record #3339 - Last Modified: 01/03/00 11:00 |
