Answers Database


M1.4 PAR - Mode pins and TDO do not show up in pad report for FPGAs


Record #3342

Product Family: Software

Product Line: FPGA Implementation

Product Part: par

Product Version: 1.4

Problem Title:
M1.4 PAR - Mode pins and TDO do not show up in pad report for FPGAs


Problem Description:
Urgency: Standard

General Description:
When using the mode pins (MD0, MD1, MD2) and/or TDO in a design
as an I/O, the pin numbers do not show up in the pad report.


Solution 1:

To insure that the signal is mapped to the correct pin, use the
library symbols MD0, MD1, MD2 and TDO. The pin number will not
show up in the pad report, but the signal will be mapped to the
specified pin. To verify this, EPIC can be opened and used to
view the signal to make sure it goes to the correct pin.

In M1.5, the .pad report will list Mode pins.




End of Record #3342 - Last Modified: 06/30/98 12:39

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!