Answers Database
LogiCORE PCI32 4000: 4062XLT BG432 -09 Ping example: Timing simulation using VSS causes failure
Record #3414
Product Family: Software
Product Line: LogiCore
Product Part: PCI Core Generator
Product Version: 2.0
Problem Title:
LogiCORE PCI32 4000: 4062XLT BG432 -09 Ping example: Timing simulation using VSS causes
failure
Problem Description:
Priority: Standard
Problem Description:
For the 4062xl-BG432-09 Ping example, running timing simulation
using VSS will result in simulation failure. The failure
is caused by the RST_N signal rising, which results in a
setup time violation in an internal flipflop. In real
circuits, since the input to the flipflop and the initial
value forced by GSR are identical, no logic failure should
ever occur. This problem is a pure simulation issue.
Solution 1:
Modify the "stimulus.vhd" file and change line 104 from:
"RST_N <= reg_rst_n after TDEL;"
to
"RST_N <= reg_rst_n after 10 ns;"
End of Record #3414 - Last Modified: 10/01/99 14:27 |
