Answers Database
A1.4/F1.4 Bitgen - Bad 5200 bitstream is created for IOB routethrus and CLB latches
Record #3438
Product Family: Software
Product Line: FPGA Implementation
Product Part: bitgen
Product Version: 1.4
Problem Title:
A1.4/F1.4 Bitgen - Bad 5200 bitstream is created for IOB routethrus and CLB latches
Problem Description:
The following two problems exist in both Alliance (A1.4) and Foundation (F1.4)
for 5200 bitgen.
1. If an IOB routethru is used, the IOB will not be configured
properly.
2. If a CLB latch is used, the clock polarity will not be properly
set for LC1, LC2 and LC3.
Solution 1:
This problem can be resolved by upgrading to A1.5/F1.5.
Solution 2:
A patch is available on the Xilinx Download area:
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/bit_5200.zip
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/bit_5200.tar.Z
This patch should be applied to both A1.4 and F1.4 products.
This fix is also included in the Core Tools #5 patch,
which also contains some other 5200 related fixes for PAR:
Solaris: ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sol17_m14.tar.Z
SunOS ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sun17_m14.tar.Z
HPUX: ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_hp17_m14.tar.Z
Win95/NT: ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_nt17.zip
End of Record #3438 - Last Modified: 10/12/98 09:56 | 
