Answers Database
2.1i, V1.5, V1.4 COREGEN, XC4000: Incorrect data on output of 4K PDA FIR and SDA FIR cores when maximum output width is not selected
Record #3493
Product Family: Software
Product Line: Coregen
Product Part: Coregen
Problem Title:
2.1i, V1.5, V1.4 COREGEN, XC4000: Incorrect data on output of 4K PDA FIR and SDA FIR cores
when maximum output width is not selected
Problem Description:
Urgency: hot
General Description:
If the maximum output data width is not selected for the
4K SDA and PDA FIR filter cores, the LSB's of the output are
trimmed, and the result is that the user will not see what they
expect for output data during simulation.
The trimming of the LSB's is inconsistent with how data bits
are trimmed in packages like Matlab and Elanix.
This is a known bug (CR 103333).
Solution 1:
This problem has been fixed in the v1.4.1 patch available on
the CORELINX web page,
http://www.xilinx.com/products/logicore/coregen/corelinx.htm
If you are unable to access this patch, the workaround is
as follows:
Select the maximum output width from the choices given to
you by the PDA or SDA FIR implementation pop-up window after
you have indicated the number of taps.
If you do not need all of the output bits, simply leave them
unconnected in your design, and they will be trimmed later
when the design is processed by Map.
End of Record #3493 - Last Modified: 09/07/99 09:28 |
