Answers Database
M1.4 Map - 5200: Map is not trimming global reset signals
Record #3525
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Product Version: 1.4.
Problem Title:
M1.4 Map - 5200: Map is not trimming global reset signals
Problem Description:
For the Synopsys Verilog flow, the current methodology for Verilog design creation is to connect all
register reset/preset signals to both the registers and STARTUP block so that functional simulation
of the reset may be performed. Upon implementation, Map should trim this signal connected to the S
TARTUP block however is not. This redundant routing is obviously not desired.
For more details see CR_README in the data directory.
Solution 1:
A fix for this problem is included in the current M1.4 Core
Applications patch available from the Xilinx Download Area:
Solaris: ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sol17_m14.tar.Z
SunOS ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_sun17_m14.tar.Z
HPUX: ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_hp17_m14.tar.Z
Win95/NT: ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/core_nt17.zip
End of Record #3525 - Last Modified: 08/18/98 18:09 | 
