Answers Database
LogiCORE PCI: Why can't an I/O Base Address Register be set to > 256 bytes on an x86 processor?
Record #3543
Product Family: Software
Product Line: LogiCore
Product Part: PCI Core Generator
Problem Title:
LogiCORE PCI: Why can't an I/O Base Address Register be set to > 256 bytes on an x86
processor?
Problem Description:
Urgency: Standard
General Description:
Why can't an I/O Base Address Register be set to > 256 bytes? on an x86 processor?
Solution 1:
Early Intel x86 microprocessors only supported 64K I/O
address space. However, early IBM PC's used the first ten
bits (SA<0-9>), thus limiting the max range of the I/O
addresses to 1K. The upper 6 lines (SA<10-15>) weren't decoded
and are treated as don't care bits. The ultimate effect of this
is the 1k space is "aliased" or repeated 64 times. The first
256 bytes of this 1K was used by the PC, leaving 768 bytes for
ISA cards that decode the 10 bits only. When the full 16 bits
were decoded on later machines, like the XT, those who made 16
bit PC cards couldn't use the initial 768 bytes or any of it's
63 other aliases, since any ten bit card would be sitting in
all 64 spaces. The only solution was to use one of the 63 256
byte aliases. So to prevent I/O space conflicts, only the first
256 byte range of each 1K of I/O space is available.
Never set an I/O Base Address Register to greater than 256 bytes on a Intel x86 system.
End of Record #3543 - Last Modified: 01/13/99 16:17 |
