Answers Database LogiCORE PCI32 4000: VHDL/Verilog synthesis/simulation with PCI LogiCORE v2.0, Synplify 5.0 & M1.4.12 Record #3547 Product Family: Software Product Line: LogiCore Product Part: PCI Core Generator Product Version: 2.0 Problem Title: LogiCORE PCI32 4000: VHDL/Verilog synthesis/simulation with PCI LogiCORE v2.0, Synplify 5.0 & M1.4.12 Problem Description: Urgency: Standard General Description: In this example, a design called 'ping' is used to demonstrate the PCI LogiCORE 2.0 in a Verilog synthesis flow. In a 'real' design, the 'ping' design is replaced with the customer application. The PCI LogiCORE 2.0 comes with example files for compiling an initiator or target with the 'ping' design. The example used in this solution uses the initiator with the 'ping' design. Solution 1: First, here is a summary of the specific steps for Synplify. The files necessary to run the PING example are shown below. This is outlined for Verilog, but you can easily correlate the same information for VHDL. The design files are available in verilog/example directory. Copy the following files to your project directory Filename Source Directory ======== ================ cfg.v verilog/example/source pcim_top.v verilog/example/source ping.v verilog/example/source pcim_lc.v verilog/src/xpci pcim_lc.sxnf verilog/src/xpci pci_lc_i.ngo verilog/src/xpci m13xp208_1.ucf verilog/src/ucf m13xp208_1.ncd verilog/src/guide The pcim_lc.sxnf must always be used. This file merges the core with the design correctly and contains needed constraints. The pci_lc_i.ngo is the PCI LogiCORE V2.0 design. The constraint file included with the PCI LogiCORE V2.0 must be used. There are 6 constraint files in the verilog/src/ucf directory. There are two UCF files for the 4013XLT, one for the 4028XLT, and three for the 4062XLT. The m13xp208_l.ncd is the guide file used to target the 4013XLT PQ208 device. Summary of changes that are specific to the Synplify Flow    1. Change the PCIM_LC.V file to include the Synplify black-box       attributes and place the attributes on the PCIM_LC component.       For Verilog, place the "/* synthesis black_box */" string after       the module declaration. For VHDL, place the       "attribute black_box of PCIM_LC : component is true;" string on       the component declaration.       NOTE: You will not need to put the black_box attribute on the       CFG or the PING hierarchy because Synplify will need to optimize       these modules.    2. Make sure to comment out those signals that are NOT used in the       user application. This should be done in the component declaration       (i.e. component PING) and the instantiation of the user app (i.e.       PING_INST : PING). This limits the number of warnings you get       for unconnected signals.    3. You'll need to selectively disable IBUF/OBUF insertion for the       PCI core since the implementation netlist contains IBUF/OBUF       declarations. However, the user pins that are used in the backend       logic need to have the I/O insertion. Do not disable "Target ->       Set Device Options -> Disable I/O Insertion". To mark the PCI I/O       ports see (Xilinx Solution 4508) details the steps of how to       selectively disable IBUF/OBUF insertion. This is applied to the       PCIM_LC.    4. Synplify 5.0.8 will automatically infer the STARTUP block       in addition to the STARTUP block already included in the       PCI_LC_I.NGO file. See (Xilinx Solution 4034) for conditions       under which Synplify will infer the STARTUP block. You'll       need to mark the PCI_RST port of PCIM_LC as the signal that is       connected to the STARTUP block.       output PCI_RST /* synthesis .ispad = 1 xc_isgsr = 1 */;       See (Xilin Solution 5023) for details.       If you have an older version of Synplify that pre-dates 5.0.8, then       this attribute is not available, and the user will have to make       manual edits to the XNF. Open your PCIM_TOP.XNF in text editor.       Perform a FIND/SEARCH for the "STARTUP" string. This line along with       the next two should be removed from your netlist.    5. Change the following line in the m13xp208.ucf:       INST "PING_INST" TNM = FFS:USER_FFS ;       To:       INST "PING_INST*" TNM = FFS:USER_FFS ;       This is because Synplify will dissolve the PING_INST hierarchy name       when it synthesizes the PING module. Every element in the PING module       will now bear the name PING_INST_ff_name and would be covered by th       "PING_INST*" in the UCF file.    6. Make sure that the configuration file is set to Zero Wait States       ENABLED. This is done by:       In Verilog: Look in the CFG.V file. Edit it to look like the       following:       -- Zero wait states       assign CFG[117] = `ENABLE ;    7. Compile the completed design following the normal directions for       the PCI Core. Directions for Synthesizing the PCI Core in Synplify 5.0    1. The Source Files list should look like this and in this order:       ping.v       cfg.v       pcim_lc.v       pcim_top.v    2. Now synthesize the design. This will generate an XNF file called       PCIM_TOP.XNF which you will use to run through the M1 tools. Place & Route of the PCI LogiCORE V2.0    1. Make sure that you set the following environment variable:       set XIL_MAP_LOC_CLOSED=true    2. Create a new project and select the PCIM_TOP.XNF as the source       input.    3. Under the implement screen, select the Options... button:       Part -> 4013xl-09-pq208    4. In the Options dialog screen select the Custom button under the       Guide Design. Select the top pull down menu. Browse to select the       part/package/speed grade NCD (i.e. m13xp208_1.ncd). Check the Match       Guide Design Exactly box. Select the correct UCF file under the       User Constraints field.    5. To make sure that timing is met, generate Post Layout Timing report       to be viewed upon completion or just run Timing Analyzer once the       design has been placed and routed. In timing analyzer select       Analyze -> Timing Constraints which should show if all timing       constraints have been met or not. Functional simulation with the PCI LogiCORE v2.0 and Verilog-XL (1) Get a list of files needed to functionally simulate the PCI LogiCORE. At the root directory of your system, type: cd verilog/example/func_sim (2) The func_sim directory will contain a file called ping_tb.f, which lists the files needed for functional simulation. The files needed for functional simulation are: verilog/src/xpci/pci_lc_i.v -Simulation model for the PCI LogiCORE v2.0 verilog/src/xpci/pcim_lc.v -Simulation wrapper for the PCI LogiCORE v2.0 verilog/example/source/cfg.v -Used for configuration of PCI LogiCORE v2.0 verilog/example/source/ping.v -User application verilog/example/source/pcim_top.v -Top-level file which connnects core to ping verilog/example/source/dumb_target.v - Dumb target RTL verilog/example/source/dumb_arbiter.v - Dumb arbiter RTL verilog/example/source/stimulus.v - Master stimulus verilog/example/source/ping_tb.v - Ping testbench For a user design, the ping.v file is replaced with the user Verilog code. At a minimum cfg.v, pcim_lc.v, and pci_lc_i.v must always be used. (3) Setup the Verilog-XL simulator to use to the UNISIM simulation library in M1.4.12. The UNISIM simulation library is located at $XILINX/verilog/src (4) Functionally simulate the PCI LogiCORE v2.0 by processing the list of files in step (2) into the Verilog-XL simulator. At the prompt, type verilog -f ping_tb.f End of Record #3547 - Last Modified: 10/01/99 14:41

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