Answers Database
LogiCORE PCI32 4000: MAP ERROR:x4kma:312 or x4kma:387- the following symbols could not be constrained to a single CLB
Record #3553
Product Family: Software
Product Line: LogiCore
Product Part: PCI Core Generator
Product Version: 2.0
Problem Title:
LogiCORE PCI32 4000: MAP ERROR:x4kma:312 or x4kma:387- the following symbols could not be
constrained to a single CLB
Problem Description:
Urgency: HOT
Problem Description I:
During mapping, ERROR:x4kma:312 or x4kma:387 may occur if the device
being targeted is a zero wait state device, yet zero wait states have not been
enabled in the configuration file.
Problem Description II:
The same error may occur during mapping LogiCORE PCI 4000 (v3.0) for the
XC4062XLA-HQ240-09 one wait state core with m1.5. This error may occur if
zero wait states have been enabled in the configuration file. The UCF file is
designed to make the M1 flow fail with the aforementioned warning if the user
forgets to disable the configuration file setting
Here is an example of the full error seen in M1.4:
ERROR:x4kma:312 - The following symbols could not be
constrained to a single CLB:
FDPE symbol "PCI_CORE/PCI_LC/PCI-CBE/IO0/OFD"
(output signal=PCI_CORE/PCI_LC/PCI-CBE/IO0/OUT)
FDCE symbol "PCI_CORE/PCI_LC/PCI-AD/IO8/OFD"
(output signal=PCI_CORE/PCI_LC/PCI-AD/IO8/OUT)
Here is an example of the full error in 1.5:
ERROR:x4kma:387 - Unable to obey design constraints which require the
combination of the following symbols into a single CLB:
HMAP symbol "PCI_CORE/PCI_LC/INITIATOR_CNTL/OE_FRAME
/$2I2735" (output signal=PCI_CORE/PCI_LC/OE_CBE)
FDCE symbol "PCI_CORE/PCI_LC/PCI-AD/IO16/OFD"
(output signal=PCI_CORE/PCI_LC/PCI-AD/IO16/OUT)
FDPE symbol "PCI_CORE/PCI_LC/PCI-CBE/IO2/OFD"
(output signal=PCI_CORE/PCI_LC/PCI-CBE/IO2/OUT)
There is a conflict for the clock enable pin. These symbols share the same
LOC parameter.
There is a conflict for the register controls. These symbols
share the same LOC attribute value, which requires them to be
mapped to the same CLB.
Solution 1:
Make sure that the configuration file is set to Zero Wait
States DISABLED. This is done as shown below:
In Verilog: Look in the cfg.v file. Edit it as shown:
// Zero wait state
assign CFG[117] = 'DISABLE ;
In VHDL: Look in the cfg.vhd file. Edit it as shown:
-- Zero wait states
cfg_int(117) <=DISABLE ;
Then rerun Synthesis before running the M1 implementation
Solution 2:
Make sure that the configuration file is set to Zero Wait
States ENABLED. This is done as shown below:
In Verilog: Look in the cfg.v file. Edit it as shown:
// Zero wait state
assign CFG[117] = 'ENABLE ;
In VHDL: Look in the cfg.vhd file. Edit it as shown:
-- Zero wait states
cfg_int(117) <=ENABLE ;
Then rerun Synthesis before running the M1 implementation
In Viewlogic: Look in the cfg.1 file. Simply edit the zero
wait state button (cfg 117) to 'ON' from 'OFF'.
End of Record #3553 - Last Modified: 04/13/99 16:24 |
