Answers Database
FPGA Express: How to avoid latch inferences
Record #3583
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Express
Product Version: 2.0
Problem Title:
FPGA Express: How to avoid latch inferences
Problem Description:
Urgency: Standard
General Description:
FPGA Express will synthesize HDL code into a variety of logic elements,
including flip flops, combinatorial gates, tri-state buffers, and latches.
For Xilinx devices, internal latches are not an efficient use of resources
because they will be built using combinatorial logic (if the particular
family targeted does not have internal latches), so it is in the user's
best interest to avoid latch inference whenever possible.
Latches are created when processes are left with certain conditions undefined,
leaving Express no choice but to infer a latch to "hold" the current value of
the process, in case the unspecified condition appears. This can happen
within CASE statements.
Solution 1:
Assign to all the same outputs in each case.
Verilog:
always @ (SEL or DIN1 or DIN2)
begin
case (SEL)
2'b00 : DOUT <= DIN1 + DIN2;
2'b01 : DOUT <= DIN1 - DIN2;
2'b10 : DOUT <= DIN1;
2'b11 :
begin
DOUT <= DIN2;
TEMP <= DIN1;
end
endcase
end
VHDL:
process (SEL, DIN1, DIN2)
begin
case SEL is
when "00" => DOUT <= DIN1 + DIN2;
when "01" => DOUT <= DIN1 - DIN2;
when "10" => DOUT <= DIN1;
when "11" =>
DOUT <= DIN2;
TEMP <= DIN1;
end case;
end process;
These examples will infer latches because the "11" case assigns two outputs,
while the others only assign one. Looking at this case from TEMP's point of
view, only one of four possible cases are specified, so it is incomplete.
Avoid this situation by assigning values to the exact same list of outputs
for each case.
Solution 2:
Include all possible cases in the case statement.
Verilog:
always @ (SEL or DIN1 or DIN2)
begin
case (SEL)
2'b00 : DOUT <= DIN1 + DIN2;
2'b01 : DOUT <= DIN1 - DIN2;
2'b10 : DOUT <= DIN1;
endcase
end
VHDL:
process (SEL, DIN1, DIN2)
begin
case SEL is
when "00" => DOUT <= DIN1 + DIN2;
when "01" => DOUT <= DIN1 - DIN2;
when "10" => DOUT <= DIN1;
end case;
end process;
These two examples will create latches because there is no provision for the
case when SEL = "11". To eliminate the latches, add another entry to deal
with this possibility.
Verilog:
2'b11 : DOUT <= DIN2;
VHDL:
when "11" => DOUT <= DIN2;
Using the DEFAULT clause (Verilog) or WHEN OTHERS (VHDL) will always work, but
may create extraneous logic. This always the safest methodology, but may
create a larger and slower design, as any unknown state will have logic to
bring it to a known state.
End of Record #3583 - Last Modified: 02/28/99 21:02 |
