Answers Database
Foundation XVHDL, CPLD: How to set global signals (tristate, set/reset, clock)
Record #3590
Product Family: Software
Product Line: Aldec
Product Part: Foundation HDL Editor
Product Version: 1.4
Problem Title:
Foundation XVHDL, CPLD: How to set global signals (tristate, set/reset, clock)
Problem Description:
Keyword: cpld, bidirectional, tristate, set, reset, GTS, GSR.
Urgency: Standard
General Description:
In CPLD design, you can assign a signal to be global set/reset,
output enable, or clock by attaching a global attribute.
How is this done with Foundation XVHDL?
This is documented in Foundation help.
Solution 1:
In Foundation Project Manager, click on help->Foundation help
contents. The attributes for these global signal are documented
in 2 places:
1. Under Techniques, CPLD Design Techniques->Global Nets:
Clock, 3-state, Set/Reset.
2. Under Reference, CPLD attribute->CPLD attributes used
in VHDL files.
The attributes are set as follows:
-- Declare BUFG attribute
attribute bufg: string;
-- For global clock:
attribute bufg of my_clock : signal is "CLK";
-- For global tristate output or output enable
attribute bufg of my_enable : signal is "OE";
-- For global set/reset.
attribute bufg of my_reset : signal is "SR";
End of Record #3590 - Last Modified: 01/03/00 11:00 |
