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SYNPLIFY: How to invert the reset (GSR/GR) pin on the STARTUP block in HDL?
Record #3594
Problem Title:
SYNPLIFY: How to invert the reset (GSR/GR) pin on the STARTUP block in HDL?
Problem Description:
Urgency: Standard
General Description: How to acces an active low GSR
(global set/reset) for xc4000e/x or GR (global reset) for
xc5200 on the STARTUP block?
Note: For xc3000 devices, the global reset signal is a
dedicated pin on the device. Also, all flip-flops and latches
reset to 0 after configuration.
Solution 1:
By default, GSR/GR pin is active high. To change the polarity of
these signals in your VHDL or Verilog code, instantiate or infer
an inverter to the net that sources the GSR/GR pin of the STARTUP
block.
The inversion will be absorbed inside the STARTUP block; a function
generator will not be used to generate the inverter.
Since the STARTUP block doesn't have any outputs that are being used
in this example, the noprune property is declared in library file so
that the compiler doesn't remove the STARTUP block.
See (Xilinx Solution 2370) for reference to GTS in a Verilog design.
See (Xilinx Solution 1670) for reference to the outputs
(DONEIN, Q1Q4, Q3, Q2) on the STARTUP block.
Solution 2:
// XC4000 -- Verilog code for active low reset
// This will work for XC5200, though the reset signal on the startup
// block is labeled GR. Synplify will map GSR signal name to GR in
// the netlist.
`include "/products/synplify.ver3_0/lib/xilinx/xc4000.v"
module use_active_low_gsr (reset);
input reset;
// the signal reset initializes all registers using the
// global STARTUP signal
STARTUP U1 (.GSR (!reset));
endmodule
Solution 3:
-- XC4000 -- VHDL code for active low reset
-- This will work for XC5200, though the reset signal on the startup
-- block is labeled GR. Synplify will map GSR signal name to GR in
-- the netlist.
library IEEE;
use IEEE.std_logic_1164.all;
library xc4000;
use xc4000.components.all;
entity use_active_low_gsr is
port (
reset : in STD_LOGIC
);
end use_active_low_gsr;
architecture xilinx of use_active_low_gsr is
begin
-- the signal reset initializes all registers using the
-- global STARTUP signal
U1 : STARTUP port map (GSR => not(reset));
end xilinx;
End of Record #3594 - Last Modified: 12/22/98 10:25 |
