Answers Database
MAP, PAR: Does Map or PAR insert global buffers on high fanout nets and/or unbuffered clock nets?
Record #3657
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Problem Title:
MAP, PAR: Does Map or PAR insert global buffers on high fanout nets and/or unbuffered clock
nets?
Problem Description:
Urgency: standard
General Description:
MAP, PAR: Does Map or PAR insert global buffers on high fanout
nets and/or unbuffered clock nets?
Solution 1:
4000E/L:
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No global buffer insertion
4000EX:
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The router for 4000EX/XL/XV will use any available global
buffer sites as routethrus for clock nets which are not
already buffered. If additional global buffers are left
over after all clock nets are allocated, they may also be
inserted on high fanout nets.
The key element in the scoring is how many K pin loads
are on the net. Because the placer and router share a
common scoring object for this, the placer can locate the
net's driver close to the selected global buffer site to
minimize overall routing delays.
Virtex:
-------
Virtex software will add global buffers to clock nets
End of Record #3657 - Last Modified: 04/03/98 17:11 |
