Answers Database
M1.4 CPLD Fitter: Combinatorial logic duplicated with multilevel logic optimization
Record #3730
Product Family: Software
Product Line: CPLD Implementation
Product Part: hitop
Product Version: 1.4
Problem Title:
M1.4 CPLD Fitter: Combinatorial logic duplicated with multilevel logic optimization
Problem Description:
Urgency: Standard
General Description:
The CPLD Fitter may duplicate combinatorial logic (2 inpus OR gates) feeding control
signals (CLK, SR, OE, CE) during multi-level optimization increasing
the macrocell count.
Solution 1:
A fix is available for this problem in the latest CPLD Tools
update available on the Xilinx Download Area:
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/cpld_sol10_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/cpld_sun10_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/cpld_hp10_m14.tar.Z
ftp://ftp.xilinx.com/pub/swhelp/M1.4_alliance/cpld_nt10_m14.zip
These update files also include the changes from previous cpld updates.
All zip files are created using WinZip. To obtain this utility,
access WinZip's web site at http://www.winzip.com
Solution 2:
IF you run into this situation, you can resolve the issue in
either of two ways.
1. Turn off multi-level logic optimization from the Advanced
optimization tab in the Design Manager, XC9500 template. This
may cause other optimization/fitting problems.
2. Use the KEEP attribute on the 2 inpit OR gates feeding the
control logic. This is a better solution.
End of Record #3730 - Last Modified: 08/26/98 17:02 |
