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 MAP M1.4: ABEL blocks in FPGA not optimized, result in high utilization (ERROR:x4kma:253 - The design is too large for the given device...)   Record #3768
 
Product Family:  Software
 Product Line:  FPGA Implementation
 
 Product Part:  map
 
 Product Version:  1.4
 
 Problem Title:
 MAP M1.4: ABEL blocks in FPGA not optimized, result in high utilization (ERROR:x4kma:253 -
The design is too large for the given device...)
 
 
 
 Problem Description:
 
 
 Urgency: Standard
 
 General Description:
 
 Targetting an FPGA with a design that contains ABEL, the ABEL
 blocks may not be optimized.  In some cases, this may cause
 the design not to fit at all.  If the Design Manager GUI is
 used, one may notice that M1.3 produced better results than a
 later version.
 
 Please note that ABEL is not recommended for FPGA designs.
 There are limitations to the EDIF synthesizer and cannot
 utilize all the features of the FPGA architecture.  The fact
 that M1 does optimize XABEL blocks for FPGA's by default is
 further evidence that VHDL or Verilog is the preferred HDL
 language when targetting FPGA's.
 
 
 Solution 1:
 
 
 The EDIF netlist generated by XABEL contains the OPTIMIZE
 attribute set to BALANCE.  This is the only setting which the
 XABEL synthesizer allows.  A value of "area" will optimize the
 logic.
 
 In a UCF file, apply the OPTIMIZE attribute on the instances
 of the ABEL blocks in the design.
 For example, the instance U1 may represent a block which
 originated from ABEL synthesized code.	Add the following
 statement to the UCF file.
 
 INST U1 OPTIMIZE = AREA;
 
 The OPT_EFFORT attribute may also be used in conjunction with
 the OPTIMIZE attribute.
 
 INST U1 OPT_EFFORT = HIGH;
 
 Refer to the Libraries Guide for more information on attributes.
 
 Note: The Metamor VHDL compiler allows to choose the
 optimization setting (area, speed, balance).
 
 
 
 Solution 2:
 
 
 Alternatively, the optimization style and effort may be applied
 to the entire design.  This may be the only way of specifying
 these attributes for a pure-ABEL FPGA design, but not
 recommended for a design that contains very little ABEL code
 as this may increase the compile time without improving the
 overall quality of results.
 
 To do this, apply the "-os" and "-oe" switches to MAP.
 
 
 
 
 End of Record #3768 - Last Modified: 07/28/98 14:41
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