Answers Database
Foundation, MAP: Excessive logic removed (trimmed) from a design captured in Foundation schematic.
Record #3821
Product Family: Software
Product Line: Aldec
Product Part: Foundation Schematic Capture
Product Version: 1.4
Problem Title:
Foundation, MAP: Excessive logic removed (trimmed) from a design captured in Foundation
schematic.
Problem Description:
URGENCY: Standard
GENERAL DESCRIPTION:
Excess logic can get stripped from a design if a customer uses I/O terminals to
define top-level I/O on a schematic rather than using IPADs and OPADs from the
Xilinx Unified Libraries.
The stripping actually only occurs on the clock buffers. In the trimming section of
the Map Report the clocks will be defined as sourceless.
This occurs because ngdbuild will automatically insert IPADs in front of IBUFs, even if these IPADs
do not exist in the EDIF netlist.
Solution 1:
The resolution is to always use IPADs and OPADs, and not I/O terminals to represent the pins of a X
ilinx device. I/O terminals should ONLY be used to make
connections between levels of hierarchy.
Note: In F1.5, I/O terminals have been renamed to Hierarchy Connectors to help
alleviate inappropriate use of them.
End of Record #3821 - Last Modified: 08/06/98 11:54 |
