Answers Database
NGD2VER/NGD2VHDL: Bus indexes are always declared in descending order within simulation netlist
Record #3852
Product Family: Software
Product Line: FPGA Implementation
Product Part: ngd2ver
Product Version: 1.5is2
Problem Title:
NGD2VER/NGD2VHDL: Bus indexes are always declared in descending order within simulation
netlist
Problem Description:
Urgency: Standard
General Description:
Currently the Xilinx Alliance HDL netlisters, NGD2VHDL and NGD2VER,
will write out bus indexing styles in Little Endian style. This means that it
will always write out buses as the largest number bit being the MSB (Most
Significant Bit) of the bus regardless of how the bus name was origionally
coded. The reason for this is that bus index style is not always reflected
in the input EDIF or XNF netlist to M1 therefore it is currently not possible
to determine which bus indexing style was origionally used in the HDL code.
Since it is most common to name buses with the largest bit number
representing MSB, that is how the simulation netlist is always written out.
If a Big Endian style (smallest number bit is declared as MSB) was used for
bus naming and brought through the M1 tools, the simulation netlist will
remain functionally correct however the testbench used for RTL simulation
can no longer match the testbench used for timing simulation since the bus
indexing will appear reversed for the Big Endian declared buses.
Xilinx is working with the various synthesis vendors to correct this problem
in the future, however, currently it is not possible to fix this problem.
Solution 1:
Since the XNF netlist is flat and so are some of the CAE vendors'
EDIF netlists for an input design (whether schematic or synthesis),
it is difficult to extract the order of the buses. Thus the NGD
database has no way to determine the ordering, all netlists
generated by the backend netlisters also have no way to extract
the ordering of the busses. Therefore, Xilinx assembles the bus in
the following form:
input/output [higher_number:lower_number] bus_name;
The main problem lies with the fact that testbenches passing
simulus or monitoring waveforms of buses as a whole should be
aware of the default bus ordering. It is generally suggested to
always code the design using the largest bit number as MSB.
An example in VHDL for this is to always use the DOWNTO syntax
when declaring a bus:
MY_BUS: in STD_LOGIC_VECTOR(3 DOWNTO 0);
For Verilog, simply declare the largest bit number first in the bus index
notation:
input [3:0] MY_BUS;
This will allow a consistent bus naming index syles ebtween the RTL
code and netlist produced by NGD2VER/NGD2VHDL netlister.
Solution 2:
If it is not possible to code the origional HDL code using the Little
Endian bus indexing convention, then either seperate testbenches.
One for RTL and the other for Timing simulation or a function needs
to be created in the testbench to reverse the bit ordering of Big
Endian style buses for the timing simulation so that they match the
bus ordering of the RTL simulation.
End of Record #3852 - Last Modified: 06/29/99 14:57 |
