Answers Database Foundation F1.4, Translate: Where does the &__A__ net name in my warning come from? Record #3895 Product Family: Software Product Line: Aldec Product Part: Foundation Schematic Capture Product Version: 1.4 Problem Title: Foundation F1.4, Translate: Where does the &__A__ net name in my warning come from? Problem Description: Urgency: Standard General Description: When running through the Xilinx Implementation tools with Foundation, Ngdbuild (translate) produces warnings/errors regarding nets named similar to: &__A__17 <-- The number may be different. The problem is that these nets do not make sense to the user because he/she did not name any nets in the design like this. How can one debug this problem? Solution 1: The Foundation edif netlist generator labels unnamed busses using this form (&__A__#). Depending on the Warnings/Errors, the problem lies with the busses defined by the hierarchy of the message. If you only have one bus at that specified hierarchy, then work with that bus to resolve the issue. To avoid the default naming, be sure to label each bus. For troubleshooting, if after labelling each bus, you continue to have default bus labels (&__A__#) in warnings/errors, you can export your design as an xnf netlist. Do this in the Foundation schematic editor: 1. In the schematic editor, from the top level sheet, select     Options - Export Netlist. 2. Then select the file type as Xilinx and select the top level     .alr or .alb file. 3. Click on Open. This will generate .xnf netlists for the design. 4. Move the top-level edif from the working directory (it can     be deleted). 5. Run the implementation tools by starting the Design Manager.     Do not start the Design Manager through the Foundation     Project Manager, instead, goto Start - Programs - Xilinx...     - Design Manager. 6. Create a new project. Point to the top-level xnf file as the design file and give a different nam e for the working directory (eg ...\xproj -> ...\xproj2). 7. Run through the implementation. The Warning/Error messages should now point to specific bus names, rather than the default &__A__# l abels. Use these specific names to debug the design. Some things to look for: 1. Make sure that when connecting a bus to a macro, that the     bus has the correct number of bits for the macro pin. 2. Make sure that if you tap off bits of a bus, and you use the     remaining bits in a macro, that the new segment of bus,     after the tapping, has a label with the correct bit width. 3. Make sure that if a bus is connected to a macro pin, that     the full bus width is used within the macro, rather than     just part of the whole bus that is connected to the pin. It     is best to reduce the macro pin bus width rather than drop     the unused bits within the macro. End of Record #3895 - Last Modified: 05/27/98 16:34

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