Answers Database
FPGA Express VHDL: Type mismatch on left and/or righ operand of binary operator. (VSS-523)
Record #3900
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Express
Product Version: 2.1.3
Problem Title:
FPGA Express VHDL: Type mismatch on left and/or righ operand of binary operator. (VSS-523)
Problem Description:
Urgency: Standard
General Description:
When compiling a VHDL file that contains binary operation on bus signals, the
following error may occur:
Error: <path to vhdl file> line <line number>
Type mismatch on left and/or right operand of binary operator. (VSS-523)
This error is due to a missing library.
Solution 1:
In the VHDL file, be sure to include the following line in the library section:
use IEEE.std_logic_unsigned.all;
End of Record #3900 - Last Modified: 11/05/98 14:34 |
