Answers Database
XC4000E/EX/XL/XV: Is it possible to implement a "true" dual port RAM in a Xilinx FPGA?
Record #3964
Product Family: Documentation
Product Line: FPGA Apps.
Product Part: XC4000 Edge Trig/Dual Port RAM
Problem Title:
XC4000E/EX/XL/XV: Is it possible to implement a "true" dual port RAM in a Xilinx FPGA?
Problem Description:
Urgency: standard
General Description:
Is it possible to implement a "true" dual port RAM in a Xilinx
FPGA?
Solution 1:
Currently the only "dual port RAM" structures supported
in Xilinx FPGAs are available on XC4000E/EX/XL/XV parts.
The Xilinx XC4000 RAM structure is not a "true" symmetrical
dual-port RAM. A "true" dual-port RAM would have two
independent ports, each capable of being read and written
independently of the other port. In the XC4000 dual
port RAM, one of the ports is read-only (the F output, SPO).
As shown on page 4-16 of the 1998 databook, there is one
common write address to both LUTs, but this write address
is used as the read address for the F output. The G
output has its own independent read address, however.
Luckily, this structure is good enough for almost all
dual-port applications, and is particularly suited to FIFOs.
True dual port RAM will be available in the Virtex
architecture in the form of block RAM.
End of Record #3964 - Last Modified: 08/13/98 19:40 |
