Answers Database
FPGA Express 2.0.x: Instantiating I/O in Verilog.
Record #3999
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Express
Product Version: 2.0.3
Problem Title:
FPGA Express 2.0.x: Instantiating I/O in Verilog.
Problem Description:
Urgency: Standard
General Description:
This solution record shows how to manually instantiate I/O cells in Verilog.
FPGA Express 2.x and older can insert all of the I/O in a design or none at all,
so if any I/O are instiated in a design, all of the I/O must be instantiated.
FPGA Express 3.x can insert unspecified I/O; you can instantiate some of the
I/O and let Express insert the rest.
Solution 1:
Input signals
1. IBUF
// IBUF instantiation
IBUF INPUTSIG_IBUF (.I(INPUTSIG_PI), .O(INPUTSIG));
INPUTSIG can be connected to internal logic.
The following can be used in a UCF file to lock the pin.
NET INPUTSIG_PI LOC=Pxx;
2. IFD
// IFD instantiation
IFD DATAIN_IFD (.D(DATAIN_PI), .C(CLK), .Q(DATAIN_R));
DATAIN_R can be connected to internal logic.
The following can be used in a UCF file to lock the pin.
NET DATAIN_PI LOC=Pxx;
Solution 2:
Output signals
1. OBUF
// OBUF instantiation
OBUF OUTPUTSIG_OBUF (.I(OUTPUTSIG), .O(OUTPUTSIG_PO));
OUTPUTSIG can be connected to internal logic.
The following can be used in a UCF file to lock the pin.
NET OUTPUTSIG_PO LOC=Pxx;
2. OFD
// OFD instantiation
OFD DATAOUT_OFD (.D(DATAOUT), .C(CLK), .Q(DATAOUT_PO));
DATAOUT can be connected to internal logic.
The following can be used in a UCF file to lock the pin.
NET DATAOUT_PO LOC=Pxx;
2. OBUFT
// OBUFT instantiation
OBUFT DATAOUT_OBUFT (.I(DATAOUT), .T(CONTROL), .O(DATAOUT_PO));
DATAOUT can be connected to internal logic.
Note: The OBUFE macro cannot be instantiated. The signal connected to the T
control pin must be inverted to act as an OBUFE.
Solution 3:
Clock signals
1. BUFG
This example shows how to instantiate a global buffer being driven directly by
an input signal. This involves a modification to the resulting XNF netlist
because a global buffer can be driven by an internal node as well as by an
external input signal.
(If directly driving the global buffer is not desired, and having the signal
go through an IBUF then a BUFG is wanted instead, the previous IBUF example
can be used followed by instantiating a BUFG, and there is no need to modify
the XNF.)
// BUFG instantiation
BUFG CLK_BUFG (.I(CLK_PI), .O(CLK));
In the XNF netlist, the following line will appear towards the end of the file.
SIG, CLK_PI, PIN=CLK_PI
Replace this line with the following.
EXT, CLK_PI, I
CLK can be connected to internal logic.
The following can be used in a UCF file to lock the pin to a clock IOB.
NET CLK_PI LOC=Pxx;
End of Record #3999 - Last Modified: 09/03/99 13:50 |
