Answers Database
M1.5i/2.1i :Post Layout Timing Report: No skew warning given for internal clocks
Record #4028
Product Family: Software
Product Line: FPGA Implementation
Product Part: Timing Analyzer
Product Version: 1.5
Problem Title:
M1.5i/2.1i :Post Layout Timing Report: No skew warning given for internal clocks
Problem Description:
Urgency: Standard
General Description: TRCE/Timing Analyzer does not report skew by default.
Solution 1:
There are three ways for TRCE/Timing Analyzer to report clock skew.
1- Place a PERIOD constraint on the clock net. Clock skew is automatically reported with a PERIOD co
nstraint.
2- Set the following environment variable:
XILINX_DOSKEWCHECK = 1
3- Run TRCE via the command line with the -skew option.
End of Record #4028 - Last Modified: 07/13/99 15:57 | 
