Answers Database
M1.x: Is there a way to access vertical longlines in FPGA (with ucf or pcf constraint)?
Record #4085
Product Family: Documentation
Product Line: FPGA Core
Product Part: docs
Problem Title:
M1.x: Is there a way to access vertical longlines in FPGA (with ucf or pcf constraint)?
Problem Description:
Urgency: Standard
General Description:
There is no specific constraint that will force the
use of a particular routing resource, unless you make a
hard macro.
Solution 1:
Here are some possibilites:
1) Use timespecs
2) Align logic using given signal into column (using RLOCs/LOCs). This
will encourage use of vertical longlines.
3) Use PCF constraint: NET my_net PRIORITIZE = 90;
This, along with timespec, will encorage use of longlines.
4) Modify the design in EPIC to use longlines.
End of Record #4085 - Last Modified: 05/26/99 07:36 |
