Answers Database
Orcad Express: ROM outputs remain low in functional simulation
Record #4120
Product Family: Software
Product Line: OrCAD
Product Part: simulate
Product Version: 6.0
Problem Title:
Orcad Express: ROM outputs remain low in functional simulation
Problem Description:
Urgency: Standard
General Description: When trying to perform a functional simulation of a
Xilinx design containing ROMs, the ROM outputs remain low, regardless
of the address accessed.
Solution 1:
In Simulate v6.0, the Convert XNF to VHDL command on the Tools menu
ignores all part attributes such as ROM initialization. Xilinx ROMs are
initialized in the schematic by the OPTIONS_1 property as INIT=<value>.
As a workaround when using ROMs in a Xilinx design, translate the .XNF
files with the Timing Simulation option selected.
End of Record #4120 - Last Modified: 08/26/98 12:08 |
