Answers Database
FPGA Express: Subpaths containing pads grouping incorrectly written by Express
Record #4122
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Express
Product Version: 2.1.1
Problem Title:
FPGA Express: Subpaths containing pads grouping incorrectly written by Express
Problem Description:
Urgency: Standard
General Description:
The Express Constraints Editor can be used to create timespecs to be passed on
to the place and route tools. Beyond the generic path specifications, users
can create subpaths (in the Paths tab) to furthur constrain their design.
However, if a subpath contains a group of pads as an endpoint, Express will
use the generic "pads" keyword in the timespec definition rather than creating
a new subgroup of pads. The design may become overconstrained as more pads
than expected will be contained in the timespec.
This issue has been fixed in FPGA Express 3.2 and Foundation 2.1i.
Solution 1:
First, remove the incorrect spec in the Express Constraints Editor to be sure
that it is not being applied during place and route.
Then, to create a correct timespec for this subpath, use the Xilinx Constraints
Editor. Group the pads by selecting the "Group by Elements" button under the
Advanced tab and using the pads filter. Create flip-flop, latch or RAM groups
in the same manner. Then use the "Multi-cycle Paths" button to create the
timespec.
End of Record #4122 - Last Modified: 07/26/99 16:30 |
