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Orcad Capture: Recommended design flow with Capture v7.10 and Xilinx M1
Record #4138
Problem Title:
Orcad Capture: Recommended design flow with Capture v7.10 and Xilinx M1
Problem Description:
Urgency: Standard
General Description:
The following information has bee provided by Orcad as a suggested flow
for designing with Orcad Capture 7.10 and Xilinx M1 tools.
For more information see the Orcad WEB page http://www.orcad.com/techserv /
Solution 1:
Recommended design flow with Capture v7.10 and Xilinx M1
1.Create your schematics with the appropriate Xilinx symbol libraries.
\orcadwin\express\library\xil_m1\xc3000\*.olb and *.edn
\orcadwin\express\library\xil_m1\xc4000\*.olb and *.edn
\orcadwin\express\library\xil_m1\xc4000e\*.olb and *.edn
\orcadwin\express\library\xil_m1\xc5200\*.olb and *.edn
\orcadwin\express\library\xil_m1\xc7000\*.olb and *.edn
\orcadwin\express\library\xil_m1\xc9000\*.olb and *.edn
2.Add M1 constraints using net or part properties as described in the
"Xilinx" topic of the Express online help.
3.Use Create Netlist (on the Tools menu) to generate EDIF 2 0 0 output.
Be sure to select the Output pin names, Output net properties and
Output part properties options.
4.Open the XACTstep M1 Design Manager.
5.Adjust Implementation Options, Interface tab, Translate Options.
Specify a Macro Search Path to reference the OrCAD provided .\\*.edn
files (listed below).
6.Create a new Project and specify the EDIF netlist created by Capture
as the Input Design.
Note: LogiBLOX integration is not available in Capture. Modules
created by LogiBLOX must be represented by component instances
in RTL or custom parts in schematics. Simulate v6.x is not
compatible with any models developed for Xilinx M1.
End of Record #4138 - Last Modified: 09/03/98 08:11 |
