Answers Database
M1.5i/2.1i: TRCE reports timing loop for Virtex designs with DLL's
Record #4162
Product Family: Software
Product Line: FPGA Implementation
Product Part: trce
Problem Title:
M1.5i/2.1i: TRCE reports timing loop for Virtex designs with DLL's
Problem Description:
Urgency: Standard
General Description:
TRCE is reporting that the DLLs are part of timing loop and
disables timing through them. Here is an example of a TRCE
report.
"2767 circuit loops found and disabled",
This message refers to the number of potential paths through
the DLL feedback connections that are not analyzed. These
would be clock paths that pass back through the DLL, the
feedback input, and back to the DLL. There's probably one
of these for every register in the design.
Solution 1:
Currently there is no way to disable the message. The user can
simply ignore the message.
End of Record #4162 - Last Modified: 07/13/99 15:58 |
