Answers Database
A1.5/F1.5 XC3000 Map - GCLK is connected to non clock pin error - ERROR:x3kma:192
Record #4184
Product Family: Software
Product Line: FPGA Implementation
Product Part: map
Problem Title:
A1.5/F1.5 XC3000 Map - GCLK is connected to non clock pin error - ERROR:x3kma:192
Problem Description:
Urgency: Standard
General Desciption:
The customer has a oscilator driving the gclk, which drives
several flip flops, which divide the clock, which drives the
aclk. Both gclk and aclk drive other flip flops in the design. With this setup, the following erro
r occurs in map:
ERROR:x3kma:192 - GCLK symbol "$1I228" (output
signal=CLK7MEG) has an output signal that is connected
to non-clock pins, which makes it unconfigurable as
a GCLK (global clock) buffer; other design elements
prevent this buffer from being swapped with the ACLK
(alternate clock) buffer. Note that the GCLK signal
can only be connected to clock pins within the device;
the ACLK buffer must be used if the output signal is to
be connected to non-clock pins.
Solution 1:
The workaround is to swap the ACLK and GCLK buffers or if
there is no ACLK buffer in the design, change the GCLK to
an ACLK buffer.
End of Record #4184 - Last Modified: 09/26/98 16:05 |
