Answers Database
M1.5i/2.1i: Timing Report: There is no negative offset, setup, or hold time
Record #4188
Product Family: Software
Product Line: FPGA Implementation
Product Part: Timing Analyzer
Product Version: 1.5
Problem Title:
M1.5i/2.1i: Timing Report: There is no negative offset, setup, or hold time
Problem Description:
Urgency: Standard
General Description: When a clock has been placed on local routing,
the clock delay can be greater than the input path delay. If an
OFFSET constraint is placed on the input in question TRCE/Timing
Analyzer will report a negative OFFSET. Similiar results can be seen
with setup and hold times.
Solution 1:
Another solution is to add some delay to the data path. This can be
done by moving the flip-flop farther away from the IOB.
Solution 2:
The resolution is to place a TIMESPEC on the clk net. This will cause
the tools to evaluate the delay on the clock line.
Example:
TIMESPEC TS01 = FROM PADS(CLK) TO FFS 10ns;
Where CLK is the net name between the pad and the buffer.
End of Record #4188 - Last Modified: 09/16/99 12:16 |
