Answers Database


M1.5i/2.1i: TRCE reports only three paths per timing constraint by default/no limit: How to increase it.


Record #4205

Product Family: Software

Product Line: FPGA Implementation

Product Part: trce

Product Version: 1.4

Problem Title:
M1.5i/2.1i: TRCE reports only three paths per timing constraint by default/no limit: How to increase it.



Problem Description:
Urgency: Standard

General Description: The default in TRCE reports only three paths
per timing constraint. There is a way to increase the number of
paths per timing constraint in the Timing Analyzer report.


Solution 1:

In Timing Analyzer click on Options -> Report Options and specify
the "limit report to" number to the number of paths you want to see
per constraint. Or specify on the command line of 'trce -v 15'.




End of Record #4205 - Last Modified: 10/13/99 10:36

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!