Answers Database


F1.4, F1.5 Timing Simulation: Preserving Hierarchy for Foundation timing simulation


Record #4216

Product Family: Software

Product Line: Aldec

Product Part: Foundation Logic Simulator

Product Version: 1.4

Problem Title:
F1.4, F1.5 Timing Simulation: Preserving Hierarchy for Foundation timing simulation


Problem Description:
Urgency: Standard

General Description:

By default, back-annotated netlists are
flattened by the ngd2edif utility which is run by the Flow Engine.
  It is possible to generate a netlist that preserves hierarchy.


Solution 1:

* In the Foundation Project manager, select Tools -> Checkpoint
   Simulation. (In F1.5, Tools -> Simulation/Verification ->
   Checkpoint Gate Simulation Control)
* The Checkpoint Simulation Dialog box will appear.
* Select the desired Version and highlight the .NGA file.
* De-select the Flat Netlist box, and click on Ok. This
   re-runs ngd2edif with a switch that preserves hierarchy, and
   then launches the simulator upon completion.




End of Record #4216 - Last Modified: 08/04/98 14:39

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!