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V1.5 COREGEN: Data width is limited to 31 or less for some CORE Generator functions (Single Port RAM, Dual Port RAM, ROM, PDA FIR Filter)
Record #4227
Product Family: Software
Product Line: LogiCore
Product Part: Coregen IP Modules
Problem Title:
V1.5 COREGEN: Data width is limited to 31 or less for some CORE Generator functions (Single
Port RAM, Dual Port RAM, ROM, PDA FIR Filter)
Problem Description:
The Data width on the following functions is currently limited
to 31:
- Registered Single Port RAM
- Registered Dual Port RAM
- Registered ROM
- SDA (Serial Distributed Arithmetic) FIR filter
- Registered FIFO
On the PDA FIR filter, the input data width is limited to
24.
Solution 1:
The limitations on the input data width for these particular
modules are associated with the fact that the input
coefficient values are represented with VHDL integer data
data types. VHDL integer data types are 32 bit data
types by definition, and using 32-bit data types as inputs
in these applications may cause arithmetic overflow problems
on the outputs during behavioral simulation.
Ref. #: 104045
End of Record #4227 - Last Modified: 12/15/99 11:44 |
