Answers Database
A 1.4 UNISIM XDW : INC_DEC_UBIN_6 does not simulate correctly
Record #4239
Product Family: Software
Product Line: Synopsys
Product Part: xsi-libs
Problem Title:
A 1.4 UNISIM XDW : INC_DEC_UBIN_6 does not simulate correctly
Problem Description:
Functional simulation is fine but post-synthesis simulation of
a INC_DEC_UBIN_6 counter counts 0,1,3,7,15, 15, 15.... which
is incorrect.
The reported problem is:
VARIABLE O_GlitchData : VitalGlitchDataType;
this variable is shared by all the bits, like following,
VitalPathDelay01 (
OutSignal => FUNC(0),
GlitchData => O_GlitchData,
OutSignalName => "FUNC(0)",
OutTemp => sum(0),
.......
VitalPathDelay01 (
OutSignal => FUNC(1),
GlitchData => O_GlitchData,
OutSignalName => "FUNC(1)",
OutTemp => sum(1),
.......
VitalPathDelay01 (
OutSignal => FUNC(5),
GlitchData => O_GlitchData,
OutSignalName => "FUNC(5)",
OutTemp => sum(5),
so the after bit 5, the O_GlitchData contains information
about bit 5, but the next process execution will treat this
info as of bit0's, then due to some VITLA acceleration
machanism, the precedure VitalPathDelay01 for bit0 is skipped.
so the value of bit0 is not updated, and so on for later bits
and stick to 15 later. I made a small change just declare
one O_GlithcData for each bit, then the simulation shows OK.
Solution 1:
This problem has been fixed in the Alliance 1.5 version of the
Designware simulation libraries.
If this version of the software is not availible to you, you may
get around this problem by performing a post-ngdbuild
(post-translate) simulation of the design:
ngdbuild <design>
ngd2vhdl <options> <design>
End of Record #4239 - Last Modified: 05/04/99 10:57 |
