Xilinx Answer #4283 : F1.4 Simulator: Simulating FPGA Express Netlist returns Warning 9218: unknown pin name

Answers Database

F1.4 Simulator: Simulating FPGA Express Netlist returns Warning 9218: unknown pin name

Record #4283
Product Family: Software

Product Line: Aldec

Product Part: Foundation Logic Simulator

Product Version: 1.4

Problem Title:

F1.4 Simulator: Simulating FPGA Express Netlist returns Warning 9218: unknown pin name

Problem Description:
Urgency: Standard

General Description:

When loading a Spartan .xnf from FPGA Express in the
Foundation Logic Simulator, one of the following warnings occur

Warning 9218: LDNODE: <your register name>(FDCE).GR - Unknown pin name
Warning 9218: LDNODE: <your register name>(IFD).GR - Unknown pin name
Warning 9218: LDNODE: <your register name>(IFD).CE - Unknown pin name

Solution 1:

The XNF file is valid. Running through the Xilinx Design
Manager Implementation tools creates valid bitstreams.

To functionally simulate the design, the design must first be
run through the Translate phase of the Implementation Tools,
then Checkpoint Simulation must be performed.

* Invoke the Design Manager by selecting the Implement button in
    the Project Manager.
* Select Design -> New Version
* Select Design -> New Revision
* Invoke the Flow Engine by clicking on the Flow Engine icon in
    Design Manager.
* Click the Step button in the Flow Engine to advance the flow through
    just the Translate phase of the flow.
* Close the Flow Engine and return to the Project Manager
* Select Tools -> Checkpoint Simulation.
* Select the .NGD file of the Ver/Rev you just created.
* The Netlist will be translated and the design will be loaded in
    the Simulator.

End of Record #4283 - Last Modified: 01/05/99 16:26

For the latest news, design tips, and patch information on the Xilinx design environment, check out the Technical Tips!