Answers Database
Timing Summary: What do the design statistics mean, maximum/minimum arrival input/output time
Record #4313
Product Family: Software
Product Line: FPGA Implementation
Product Part: Timing Analyzer
Problem Title:
Timing Summary: What do the design statistics mean, maximum/minimum arrival input/output
time
Problem Description:
Urgency: Standard
General Description: At the bottom of the timing report there is a Timing
Summary, What do the Design Statistics mean?
Solution 1:
Minimum Period - Minimum Delay from any synchronous element to
another. Is also displayed in Mhz.
Maximum path delay from/to any node - Maximum delay from any
node to any other node.
Minimum input arrival time before clock - This is the minimum
global OFFSET IN BEFORE
Maximum input arrival time after clock - This is the maximum
global OFFSET IN AFTER
Minimum output arrival time before clock - This is the minimum
global OFFSET OUT BEFORE
Maximum output arrival time after clock - This is the maximum
global OFFSET OUT AFTER
End of Record #4313 - Last Modified: 07/20/99 09:33 |
