Answers Database JTAG - Can I configure FPGAs and CPLDs in a mixed JTAG chain? Record #4327 Problem Title: JTAG - Can I configure FPGAs and CPLDs in a mixed JTAG chain? Problem Description: Urgency: Standard General Description: Is it possible to configure mixed device (FPGAs and CPLDs) chains via the boundary scan interface using any software? Solution 1: The following families can be programmed with the latest revision of the software A1.5 or F1.5. This is a new feature that was not supported in previous versions of the Xilinx implementation tools, that is A1.4, F1.4 or before. The 4000, 4000E, 4000EX, 4000XL, 5200, Spartan, 4000XV, 4000XLA, 9500, 9500XL all have the capability of being programmed via the JTAG pins. The 3000 series family does not support this feature. The FPGA's support configuration via the JTAG but you cannot perform other JTAG operations such as INTEST with the Implementation software. Support for other Boundary Scan features that the hardware supports can be utilized with third party software or ATE software and equipment. Note: In order to use the JTAG pins on the FPGA you must do the following: 1. Instantiate BSCAN core in your design 2. Drive the INIT pin low on the device 3. If you want to use the readback functionality for multiple      readbacks you will need to instantiate the Readback symbol. End of Record #4327 - Last Modified: 01/10/00 17:55

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