Answers Database
FPGA Compiler Verilog: Example of how to infer "set" flip-flop when GSR is asserted
Record #4345
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Compiler
Product Version: 1998.02-1
Problem Title:
FPGA Compiler Verilog: Example of how to infer "set" flip-flop when GSR is asserted
Problem Description:
Keyword: gsr, set flip-flop, verilog
Urgency: standard
reset FF upon power-up using FPGA Compiler as the synthesis tool.
This example is also incorperating a STARTUP block so that the
global set/reset signal is brought out to a user pin.
Solution 1:
module s_n_r_ffs (global_reset, CLK, DATA_RESET, DATA_PRESET, Q_RESET, Q_PRESET);
input global_reset, CLK, DATA_RESET, DATA_PRESET;
output Q_RESET, Q_PRESET;
reg Q_RESET, Q_PRESET;
STARTUP the_reset (.GSR(global_reset));
always @ (posedge CLK or posedge global_reset)
begin: RESET_FF
if (global_reset)
Q_RESET <= 1'b0;
else
Q_RESET <= DATA_RESET;
end
always @ (posedge CLK or posedge global_reset)
begin: PRESET_FF
if (global_reset)
Q_PRESET <= 1'b1;
else
Q_PRESET <= DATA_PRESET;
end
endmodule
Solution 2:
Connect the STARTUP block to a port as well as to every FF in the design.
By connecting the same port to all FF re/presets, the RTL testbench can match
the Timing testbench in terms of the global reset.
Map will issue the following expected warning:
WARNING:baste:22 - The signal "n110" is connected to the GR/GSR (global set/reset) pin on the STARTU
P component as well as every asynchronous flip-flop set/reset in the design. Removing this signal f
rom every flip-flop in the design (leaving the STARTUP connection) will reduce the amount of routing
resources required to implement the design.
This is OK since we want that signal to be removed. Make sure to connect this signal to every infer
red FF and Latch in the design or else the signal will not get removed and redundant routing will re
sult.
End of Record #4345 - Last Modified: 05/04/99 10:55 |
