Answers Database
Foundation F1.5, ABEL: Can't synthesize or add ABEL file to HDL project
Record #4354
Product Family: Software
Product Line: Aldec
Product Part: Foundation HDL Editor
Problem Title:
Foundation F1.5, ABEL: Can't synthesize or add ABEL file to HDL project
Problem Description:
Urgency: standard
General Description:
ABEL language selection is grayed out and you cannot add the ABEL
file to the project in Project Manager.
Solution 1:
If you want to create a top-level ABEL design, you must do this in a
"Schematic" project flow. See (Xilinx Solution 4353) for more information
on doing this.
Solution 2:
If you wish to include an ABEL file in a top-level VHDL or Verilog design,
then you must instantiate the ABEL module as a black-box in the VHDL
or Verilog. The ABEL file must first be synthesized to an EDIF file, and
then this EDIF file is instantiated as the black box in the top-level VHDL
or Verilog. For more information on performing this synthesis, please see
(Xilinx Solution 4353).
End of Record #4354 - Last Modified: 07/27/99 08:37 |
