Answers Database
Foundation F1.5, HDL Editor: Can't synthesize top-level VHDL or Verilog file from HDL Editor
Record #4365
Product Family: Software
Product Line: Aldec
Product Part: Foundation HDL Editor
Problem Title:
Foundation F1.5, HDL Editor: Can't synthesize top-level VHDL or Verilog file from HDL
Editor
Problem Description:
Date: 9/98
Urgency: standard
General Description:
In Foundation F1.5, top-level VHDL or Verilog designs are created as
"HDL Flow" projects. When in the "HDL Flow," the VHDL or Verilog files in
the project are editted and syntax-checked in the HDL Editor, but are not
synthesized from within the HDL Editor. This behavior is different from
Foundation F1.4 and earlier.
Solution 1:
In order to be able to synthesize the HDL file by using the Synthesis button in the
Project Manage, the HDL file must be added to the Foundation Project. Once it is
added, you should be able to see it in the Files tab of the Project Manager. To add
a file to the project, select Document -> Add from the Project Manager.
Solution 2:
To synthesize the HDL file(s) in Foundation F1.5, you have the following
choices:
1. Click the Synthesis phase button in the project flowchart in the Project
Manager.
2. Right-click on the HDL entity/module in the Files tab, and choose
Synthesize.
3. Select Synthesis -> Synthesize from the Project Manager.
For VHDL or Verilog modules in a Schematic top-level project, you synthesize
the HDL files from within the HDL Editor by selecting Synthesis->Synthesize,
or Project -> Create Macro.
End of Record #4365 - Last Modified: 03/03/99 13:28 |
