Answers Database M1.5i/2.1i: TRACE: Information about Circuit loops reported TRCE/Timing Analyzer Record #4367 Product Family: Software Product Line: FPGA Implementation Product Part: trce Problem Title: M1.5i/2.1i: TRACE: Information about Circuit loops reported TRCE/Timing Analyzer Problem Description: Urgency: Standard General Description: When a design contains circuit loops, TRACE 1.5, will report the loop in a table. An example is given below. Xilinx TRACE, Version M1.5.19 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Design file: main.ncd Physical constraint file: main.pcf Device,speed: xc4062xl,-2 (x1_0.37 1.22 FINAL) Report level: error report, limited to 3 items per constraint -------------------------------------------------------------------------------- WARNING:bastw:170 - No timing constraints found, doing default enumeration. 875 circuit loops found and disabled. ---------------------------------------------------------------------- ! Warning: The following connections are in combinational loops, and ! ! some paths through these connections may not be analyzed. ! ! ! ! Signal Driver Load ! ! -------------------------------- ---------------- ---------------- ! ! FC1/FREQ_LAT15 CLB_R18C31.Y CLB_R18C31.C4 ! ! FC3/FREQ_LAT15 CLB_R3C34.Y CLB_R3C34.C3 ! ! FC5/FREQ_LAT15 CLB_R21C11.Y CLB_R21C11.C3 ! There are two issues associated with this report. 1- Typicially each net reported will result in several loops being reported as 'Found and Disabled'. 2- The signal reported could be one of many signals in the path. Solution 1: Both of these issues will be addressed in the next major release of the software. Also, the circuit loops that are reported are still design dependant. End of Record #4367 - Last Modified: 02/09/00 09:42

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