Answers Database
FPGA Express: How to instantiate Xilinx Library elements (primitives or macros) in your HDL
Record #4385
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Express
Product Version: 2.1.2
Problem Title:
FPGA Express: How to instantiate Xilinx Library elements (primitives or macros) in your HDL
Problem Description:
Urgency: Standard
General Description:
How does one instantiate components from the Xilinx Unified Library?
Solution 1:
All Xilinx primitives can be instantiated in a design to be synthesized by FPGA Express.
Use the Xilinx Libraries Guide to find the names of the pins.
For Xilinx macros, add the appropriate XNF file to your project. XNF files can be obtained
from the $SYNOPSYS\xilinx\macros\<family>\v6_xnf directory, where $SYNOPSYS is the
Synopsys install directory for Alliance users and the FNDTN\synth directory for Foundation
users. The xc4000e directory will work for all xc4000 series families, including Spartan and
SpartanXL.
NOTE #1: Bus pins are not delimited with brackets (i.e. BUS<3>) within these macro XNF
files; there are no delimiters (i.e. BUS3). Therefore, before reading a macro XNF into your
FPGA Express project, select Synthesis -> Options and select the "Project" tab. Change
the "Input XNF Bus style" to %s%d instead of %s<%d>.
NOTE #2: This solution does not apply for Virtex/E or Spartan2 designs. Macros for these
are not available. Moreover, with FPGA Express 3.3 and earlier, primitives will not be
recognized by Express. See (Xilinx Solution 6987) for complete details.
End of Record #4385 - Last Modified: 09/24/99 09:16 |
