Answers Database
2.1i: Constraint Editor: Can't find Clock Enable net when All Nets is selected.
Record #4461
Product Family: Software
Product Line: M1 Implementation
Product Part: Constraints Editor
Product Version: 2.1i
Problem Title:
2.1i: Constraint Editor: Can't find Clock Enable net when All Nets is selected.
Problem Description:
Urgency: Standard
General Description:
In the TPTHRU dialog, the net A_EQ_B doesn't show up,
but view the design in FPGA Editor, the net is listed.
Solution 1:
The net is connected to the CLK_EN pin (clock enable),
which is not listed under All Nets
This will be fixed in a future release of the software or
service pack.
End of Record #4461 - Last Modified: 08/02/99 09:11 |
