Answers Database
FPGA Express: Cannot have complex expression in always block sensitivity list (VE-92)
Record #4492
Product Family: Software
Product Line: Synopsys
Product Part: FPGA Express
Problem Title:
FPGA Express: Cannot have complex expression in always block sensitivity list (VE-92)
Problem Description:
Urgency: Standard
General Description:
Using a complex condition check inside an always block in Verilog is not supported by
FPGA Express. For example, the following code will result in the error below:
always @( negedge input1 or negedge input2 or posedge clock )
begin
if ( ~input1 | ~input2 )
begin
output1 <= 1'b1;
output2 <= 1'b0;
end
else
begin
output1 <= input1;
output2 <= input2 & input1;
end
end
Error: The expression in the reset condition of the 'if' statement in this 'always' block can
only be a simple identifier or its negation (near symbol ")" on line 13 in file test.v) (VE-92)
Solution 1:
Perform the combinatorial logic outside the always block, then use that intermediate signal
in the sensitivity list of the always block.
assign temp = ~input1 | ~input2;
always @( posedge temp or posedge clock )
begin
if ( temp )
begin
output1 <= 1'b1;
output2 <= 1'b0;
end
else
begin
output1 <= input1;
output2 <= input2 & input1;
end
end
End of Record #4492 - Last Modified: 11/11/99 13:25 |
