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Synopsys Design Compiler: How to specify the INIT attribute on instantiated ROM/RAM primitives
Record #4595
Problem Title:
Synopsys Design Compiler: How to specify the INIT attribute on instantiated ROM/RAM
primitives
Problem Description:
Urgency: Standard
General Description:
This Solution record describes how to specify the INIT attribute on
instantiated ROM/RAM primitives in a Synopsys Design Compiler
Verilog or VHDL design. The INIT attribute specifies the
initialized value of the component and is required on the ROM
primitives (ROM16X1, ROM32X1) if instantiated in the design.
Solution 1:
Before specifying the set_attribute command to initialize the
ROM/RAM components, the following line needs to be added to the
.synopsys_dc.setup file if it is not already there:
edifout_write_properties_list = {"instance_number" "pad_location" "part" "INIT"}
In order the specify the INIT attribute, the following line may be
placed into the Synopsys compile script before writing out the
SEDIF netlist:
set_attribute "<instance_name>" "INIT" -type string "<value>"
where <instance_name> is replaced by the instance name given to the
instantiated ROM/RAM primitive and <value> is the hex value desired
to be placed on that component.
Repeat this command for each ROM/RAM component you wish to
initialize.
End of Record #4595 - Last Modified: 05/04/99 10:53 |
