Answers Database
F1.5: State Editor generates incorrect one-hot encoded VHDL with a trap state exit logic
Record #4599
Product Family: Software
Product Line: Aldec
Product Part: Foundation State Editor
Product Version: 1.5
Problem Title:
F1.5: State Editor generates incorrect one-hot encoded VHDL with a trap state exit logic
Problem Description:
Urgency: Normal
General Description:
F1.5. When user generates a VHDL code from State Editor to
implement a one-hot encoded FSM with a trap state exit logic,
the simulation shows that the transition from illegal states
to the trap state does not work. FSM goes to proper trap state
when reset is asserted, but logic, instead of reset signal,
should force exit from any illegal states on the next clock
transition.
Solution 1:
The current workaround is to edit the VHDL code to explicitly
list all the enumerated states. However, this is quite
cumbersome if the user has large state machines.
Solution 2:
The FSM must be synthesized with the followign options
checked: "safest - all possible including illegal states".
In Foundation Project Manager, Synthesis -> Options ->
Under FSM Synthesis: check 'Safest (all possible, including
illegal, states)
End of Record #4599 - Last Modified: 06/14/99 08:49 |
