Answers Database
LOGIBLOX: How a divide-by-8 LogiBLOX CLOCK DIVIDER is implemented
Record #4602
Product Family: Software
Product Line: FPGA Implementation
Product Part: logiblox
Problem Title:
LOGIBLOX: How a divide-by-8 LogiBLOX CLOCK DIVIDER is implemented
Problem Description:
Urgency: standard
General Description:
How the LogiBLOX CLOCK DIVIDER is implemented.
Solution 1:
LogiBLOX CLOCK DIVIDERs are implemented as LFSR counters.
They are not generated with RLOCs.
EXAMPLE:
--------
How a divide-by-8 clkdiv with duty-cycle=4 is created:
CLK_OUT = Q of a DFF with input D, where
D = (CLK_OUT xor TERM_CNT), where
TERM_CNT = terminal count of a counter that counts to 4.
Basically TERM_CNT is high for one cycle every 4th cycle and toggles the DFF.
Although the divider could have been implemented as a 2-wide
binary counter, Logiblox implements it as an LFSR counter.
The reason for this is that for big counters, an LFSR counter
is much more CLB-efficient than a simple binary counter. The
2-bit wide counter could be treated as a special case,
but it is not.
Instead, it is implemented as an LFSR containing 3 flip-flops,
where:
d2 = q1
d1 = q0
d0 = q0 xor q2
This LFSR counter repeats every 7 cycles (unlike a 3-bit
binary counter which counts to 8)
The sequence is:
000
001
010
101
011
110
100
000 ...
Its term count is generated as : q2 and !q1 and !q0
To force it to act like a 4-state counter which counts
101
011
110
100
101...
The power-up state is set to 101 and additional logic is
used to force it to go to 101 when TERM_CNT is high (i.e., on
the next clock after the register is 100).
End of Record #4602 - Last Modified: 09/30/98 19:00 |
