Answers Database
VCS: time_sim.sdf:2901, SDF Error: Cannot find timing check (accSetup) in type X_FF,
Record #4611
Product Family: Software
Product Line: ViewLogic
Product Part: VCS
Problem Title:
VCS: time_sim.sdf:2901, SDF Error: Cannot find timing check (accSetup) in type X_FF,
Problem Description:
Keyword: Verilog, acchold, X_RAM
Urgency: Standard
General description:
When performing simulation using time_sim.v generated by
ngd2ver, VCS give the following errors :
time_sim.sdf:2901, SDF Error: Cannot find timing check (accSetup) in type X_FF
Solution 1:
The errors/warnings are due to the TIMINGCHECK properties in
the SDF file not matching the timing checks specified in SIMPRIM
Verilog models. The SDF file is specified for both posedge and
negedge, but the SIMPRIMS only specify posedge.
A1.5i contains the patched version of the Verilog SIMPRIM models
that include timing checks for both posedge and negedge edges
instead of just one check without any edge qualifier.
This is fixed for A2.1i.
End of Record #4611 - Last Modified: 10/26/99 10:45 |
