Answers Database
M1.5i/2.1i: Timing Analyser cannot be used to analyse a path through the asych PRE/CLR of an XC9500 FDCP
Record #4624
Product Family: Software
Product Line: FPGA Implementation
Product Part: Timing Analyzer
Product Version: 1.5
Problem Title:
M1.5i/2.1i: Timing Analyser cannot be used to analyse a path through the asych PRE/CLR of
an XC9500 FDCP
Problem Description:
an FDCP in the XC9500 family cannot be analysed using the timing
analyser. The path up to the preset or clear *is* measurable, but not
the path through the flop from the pre/clr to the output.
Solution 1:
The path delay may be calculated manually using the XC9500 timing
model:
tin + tptsr + t aoi + tout
This would be from a pad, through a buffer to the preset/clear, through
the flop, through the output buffer and to the opad.
End of Record #4624 - Last Modified: 07/13/99 16:01 |
